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August 1996
ML65244/ML65L244* High Speed Dual Quad Buffer/Line Drivers
GENERAL DESCRIPTION
The ML65244 and ML65L244 are non-inverting dual quad buffer/line drivers. The high operating frequency (50MHz driving a 50pF load) and low propagation delay (ML65244 - 1.7ns, ML65L244 - 2ns) make them ideal for very high speed applications such as processor bus buffering and cache and main memory control. These buffers use a unique analog implementation to eliminate the delays inherent in traditional digital designs. Schottky clamps reduce under and overshoot, and special output driver circuits limit ground bounce. The ML65244 and ML65L244 conform to the pinout and functionality of the industry standard FCT244 and are intended for applications where propagation delay is critical to the system design. Note: This part was previously numbered ML6582.
FEATURES
s Low propagation delay -- 1.7ns ML65244 2.0ns ML65L244 s Fast Dual 4-bit TTL level buffer/line driver with tri-state capability on the output (two 4-bit sections) s TTL compatible input and output levels s Schottky diode clamps on all inputs to handle undershoot and overshoot s Onboard schottky diodes minimize noise s Reduced output swing of 0 - 4.1 volts s Ground bounce controlled outputs, typically less than 400mV s Industry standard FCT244 type pinout s Applications include high speed cache memory, main memory, processor bus buffering, and graphics cards
BLOCK DIAGRAM
*This Part Is Obsolete
VCC 20 VCC 2G 19 1G 1
YAO 18
BO 17
YA1 16
B1 15
YA2 14
B2 13
YA3 12
B3 11
10 GND
2 AO
3 YBO
4 A1
5 YB1
6 A2
7 YB2
8 A3
9 YB3
1
ML65244/ML65L244
PIN CONFIGURATION
20-Pin SOIC, QSOP
1G A0 YB0 A1 YB1 A2 YB2 A3 YB3 GND
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
VCC 2G YA0 B0 YA1 B1 YA2 B2 YA3 B3
TOP VIEW
PIN DESCRIPTION
NAME Ai YAi Bi YBi 1G 2G GND VCC I/O I O I O I I I I DESCRIPTION Data Bus A Data Bus A Data Bus B Data Bus B Output Enable for data bus A Output Enable for data bus B Signal Ground + 5V supply
FUNCTION TABLE
1G/2G H L L
L = Logic Low H = Logic High X = Don't Care Z = High Impedance
Ai/Bi X L H
YAi/YBi Z L H
ABSOLUTE MAXIMUM RATINGS
VCC ............................................................................... -0.3V to 7V DC Input voltage ................................ -0.3 to VCC + 0.3V AC Input voltage (< 20ns) ........................................ -3.0V DC Output voltage ............................. -0.3 to VCC + 0.3V Output sink current (per pin) ................................ 120mA Storage temperature ................................ -65C to 150C Junction temperature .............................................. 150C Thermal Impedance (JA) SOIC ............................................................... 96C/W QSOP ............................................................ 100C/W
2
ML65244/ML65L244
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER
Unless otherwise stated, these specifications apply for: VCC = 5.0 5%V, TA = 0C to 70C (Note 1).
CONDITIONS MIN TYP MAX UNITS
AC ELECTRICAL CHARACTERISTICS (CLOAD = 50pF, RLOAD = 500) tPLH, tPHL Propagation delay Ai to YAi, Bi to YBi (Note 2) ML65244 ML65L244 tOE tOD CIN Output enable time 1G, 2G to YAi/YBi Output disable time 1G, 2G to YAi/YBi Input capacitance 8 1.4 1.6 10 1.7 2.0 15 10 ns ns ns ns pF
DC ELECTRICAL CHARACTERISTICS (CLOAD = 50pF, RLOAD = ) VIH VIL IIH Input high voltage Input low voltage Input high current Logic HIGH Logic LOW Per pin, VIN = 3V ML65244 ML65L244 IIL Input low current Per pin, VIN = 0 ML65244 ML65L244 IHI-Z IOS VIC VOH VOL VOFF Three-state output current VCC = 5.25V, 0 < VIN < VCC Short circuit current Input clamp voltage Output high voltage Output low voltage VIN - VOUT per buffer VCC = 5.25V, VO = GND (Note 3) VCC = 4.75V, IIN = 18mA VCC = 4.75V, IOH = 100A (Notes 4 & 5) VCC = 4.75V, IOL = 25mA (Notes 4 & 5) VCC = 4.75V (Note 4) ML65244 ML65L244 ICC
Note 1: Note 2: Note 3: Note 4: Note 5:
2.0 0.8 0.5 0.3 2.4 0.8 1.5 0.5 3.5 1.0 5 -60 -0.7 2.4 0.6 0 0 100 200 55 200 300 80 -225 -1.2
V V mA mA mA mA A mA V V V mV mV mA
Quiescent Power Supply Current
VCC = 5.25V, Freq = 0Hz, Inputs/outputs open
Limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions. One line switching, see Figure 3, tPLH, tPHL versus CL. Not more than one output should be shorted for more than a second. This is a true analog buffer. In the linear region, the output tracks the input with an offset (VOFF). For VOH, VIN = 2.7V. VOH MIN includes VOFF. For VOL, VIN = 0V, VOL MAX includes VOFF See Figure 2 for IOH versus VOH and IOL versus VOL data.
tR, tF 4ns 3V INPUT 0V 3V OUTPUT 0V 1.5V 1.5V tPLH 1.5V 1.5V tPHL
3
ML65244/ML65L244
CH1 1.00V
CH2 1.00V
10.0ns
CH1 1.00V
CH2 1.00V
10.0ns
74FCT244
+20 0 -20 -40 IOH (mA) -60 -80 -100 -120 -140 -160 -180 -200
0.5 1.0 VOL (V) 1.5 2.0 2.5
ML65244
Figure 1. Ground Bounce Comparison, Four Outputs Switching into 50pF Loads.
220 200 180 160
IOL (mA)
140 120 100 80 60 40 20 0 0.0
2.5
3.0 VOH (V)
3.5
4.0
Figure 2a. Typical VOL Versus IOL for One Buffer Output.
3.0 210
Figure 2b. Typical VOH Versus IOH for One Buffer Output.
150pF 2.5 ML65L244 2.0 ML65244 1.5 190 100pF 170 75pF 50pF
ICC (mA)
tpd (ns)
150 130 110 90 30pF
1.0
0.5 70 0.0 30 50 75 LOAD CAPACITANCE (pF) 100 150 50 10
20
30
40
50
60
70
80
90
FREQUENCY (MHz)
Figure 3. Propagation Delay (tPLH, tPHL) Versus Load Capacitance, One Output Switching.
Figure 4. ICC Versus Frequency for Various Load Capacitances, Four Outputs Switching.
4
ML65244/ML65L244
FUNCTIONAL DESCRIPTION
The ML65244 and ML65L244 are very high speed noninverting buffer/line drivers with three-state outputs which are ideally suited for bus-oriented applications. They provide a low propagation delay by using an analog design approach (a high speed unity gain buffer), as compared to conventional digital approaches. The ML65244 and ML65L244 follow the pinout and functionality of the industry standard FCT244 series of buffer/line drivers and are intended to replace them in designs where the propagation delay is a critical part of the system design considerations. The ML65244 and ML65L244 are capable of driving load capacitances several times larger than their input capacitance. They are configured so that the Ai inputs go to the YAi outputs, with the A side output enable controlled by 1G. Similarly, 2G controls the Bi inputs which go to the YBi outputs. These unity gain analog buffers achieve low propagation delays by having the output follow the input with a small offset. The output rise and fall times will closely match those of the input waveform. All inputs and outputs have Schottky clamp diodes to handle undershoot or overshoot noise suppression in unterminated applications. All outputs have ground bounce suppression (typically < 400mV), high drive output capability with almost immediate response to the input signal, and low output skew. The IOL current drive capability of a buffer/line driver is often interpreted as a measure of its ability to sink current in a dynamic sense. This may be true for CMOS buffer/ line drivers, but it is not true for the ML65244 and ML65L244. This is because their sink and source current capability depends on the voltage difference between the output and the input. The ML65244 can sink or source more than 100mA to a load when the load is switching due to the fact that during the transition, the difference between the input and output is large. IOL is only significant as a DC specification, and is 25mA.
ARCHITECTURAL DESCRIPTION
Until now, buffer/line drivers have been implemented in CMOS logic and made to be TTL compatible by sizing the input devices appropriately. In order to buffer large capacitances with CMOS logic, it is necessary to cascade an even number of inverters, each successive inverter larger than the preceding, eventually leading to an inverter that will drive the required load capacitance at the required frequency. Each inverter stage represents an additional delay in the gating process because in order for a single gate to switch, the input must slew more than half of the supply voltage. The best of these CMOS buffers has managed to drive a 50pF load capacitance with a delay of 3.2ns. Micro Linear has produced a dual quad buffer/line driver with a delay less than 1.7ns by using a unique circuit architecture that does not require cascaded logic gates. The ML65244 uses a feedback technique to produce an output that follows the input. If the output voltage is not close to the input, then the feedback circuitry will source or sink enough current to the load capacitance to correct the discrepancy.
VCC
R8
Q1
Q2 R7 R2 OUT Q4 Q6
R3 R1 IN
R4
Q3 R5
Q5
Q7
R6
GND
Figure 5. One buffer cell of the ML65244
5
ML65244/ML65L244
The basic architecture of the ML65244 is shown in Figure 5. It is implemented on a 1.5m BiCMOS process. However, in this particular circuit, all of the active devices are NPNs -- the fastest devices available in the process. In this circuit, there are two paths to the output. One path sources current to the load capacitance when the signal is asserted, and the other path sinks current from the output when the signal is negated. The assertion path is the emitter follower path consisting of the level shift transistor Q1, the output transistor Q2, and the bias resistor R8. It sources current to the output through the 75 resistor R7 which is bypassed by another NPN (not shown) during fast input transients. The negation path is a current differencing op amp connected in a follower configuration. The active components in this amplifier are transistors Q3-Q7. R3-R6 are bias resistors, and R1 and R2 are the feedback resistors. The key to understanding the operation of the current differencing op amp is to know that the currents in transistors Q3 and Q5 are the same at all times and that the voltages at the bases of Q4 and Q6 are roughly the same. If the output is higher than the input, then an error current will flow through R2. This error current will flow into the base of Q6 and be multiplied by squared to the collector of Q7, closing the loop. The larger the discrepancy between the output and input, the larger the feedback current, and the harder Q7 sinks current from the load capacitor. A number of MOSFETs are not shown in Figure 5. These MOSFETs are used to three-state dormant buffers. For instance, the feedback resistors R1 and R2 were implemented as resistive transmission gates to ensure that disabled buffers do not load the lines they are connected to. Similarly, there is a PMOS in series with R8 that is normally on but shuts off for disable. Other MOSFETs have been included to ensure that disabled buffers consume no power. TERMINATION R7 in Figure 5 also acts as a termination resistor. This 75 resistor is in series with the output and therefore helps suppress noise caused by transmission line effects such as reflections from mismatched impedances. System designers using CMOS transceivers commonly have to use external resistors in series with each transceiver output to suppress this noise. Systems using the ML65244 or ML65L244 may not have to use these external resistors.
APPLICATIONS
There are a wide variety of needs for extremely fast buffers in high speed processor system designs like Pentium, PowerPC, Mips, Sparc, Alpha and other RISC processors. These applications are either in the cache memory area or the main memory (DRAM) area. In addition, fast buffers find applications in high speed graphics and multimedia applications. The high capacitive loading due to multiplexed address lines on the system bus demand external buffers to take up the excess drive current. The needed current to skew the transitions between rise and fall times must be done without adding excessive propagation delay. The ML65244 and ML65L244 are equipped with Schottky diodes to clean up ringing from overshoot and undershoot caused by reflections in unterminated board traces.
6
ML65244/ML65L244
PHYSICAL DIMENSIONS inches (millimeters)
Package: S20 20-Pin SOIC
0.498 - 0.512 (12.65 - 13.00) 20
0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID
1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0 - 8
0.090 - 0.094 (2.28 - 2.39)
0.012 - 0.020 (0.30 - 0.51)
SEATING PLANE
0.005 - 0.013 (0.13 - 0.33)
0.022 - 0.042 (0.56 - 1.07)
0.007 - 0.015 (0.18 - 0.38)
Package: K20 20-Pin QSOP
0.338 - 0.348 (8.58 - 8.84) 20
PIN 1 ID
0.150 - 0.160 (3.81 - 4.06)
0.228 - 0.244 (5.79 - 6.20)
0.050 - 0.055 (1.27 - 1.40) (4 PLACES)
1 0.025 BSC (0.63 BSC) 0.060 - 0.068 (1.52 - 1.73) 0 - 8
0.055 - 0.061 (1.40 - 1.55)
0.008 - 0.012 (0.20 - 0.31) SEATING PLANE
0.004 - 0.010 (0.10 - 0.26)
0.015 - 0.035 (0.38 - 0.89)
0.006 - 0.010 (0.15 - 0.26)
7
ML65244/ML65L244
ORDERING INFORMATION
PART NUMBER ML65244CK ML65244CS ML65L244CK ML65L244CS SPEED 1.7ns 1.7ns 2.0ns 2.0ns TEMPERATURE RANGE 0C to 70C 0C to 70C 0C to 70C 0C to 70C PACKAGE 20-Pin QSOP (K20) 20-Pin SOIC (S20) 20-Pin QSOP (K20) (Obsolete) 20-Pin SOIC (S20) (Obsolete)
Intel, Pentium, PCI are registered trademarks of Intel Corporation. Mips, Alpha and Sparc are registered trademarks of Silicon Graphics, DEC and Sun Microsystems respectively.
(c) Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295
DS65244-01
8

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